VDP

The VDP, also known as Video Display Processor, handles all video output on the Mega Drive. The VDP is often known as the YM7101, which is derived from the Sega Master System VDP for backwards compatibility. The Master System VDP is in turn derived from the Texas Instruments TMS9918A. In most (if not all) Mega Drive models, the VDP is a dedicated large chip on the main motherboard.

It has 64 KB of VRAM, which can be used to store patterns (also known as art) plane and sprite name tables, as well as horizontal scroll data. The benefit of storing name tables and H-Scroll in VRAM is that you can decide where this data is stored, but leaves less room for art. The VDP has 64 bytes of 9-bit RAM to store palettes. This special area of the VDP is known as CRAM, or Colour RAM.

The VDP has the capability of displaying up to 80 sprites on-screen, as well as the A and B planes, and the Window plane. The window plane can be used as a replacement for the A plane in some circumstances. It can also support 64 on-screen colours at any time, as well as scrolling the entire screen or specific parts of it horizontally and vertically. There is also multiple registers that control how the VDP is configured, which are written to the control word as 16-bit words.

Accessing the VDP

To access the VDP, you must use a special area of I/O memory. Below is a map of the VDP's IO memory, starting at $C00000:

$C00000	Data Port
$C00002	Data Port (Mirror)
$C00004	Control Port
$C00006	Control Port (Mirror)
$C00008	H/V Counter
$C0000A	H/V Counter (Mirror)
$C0000C	H/V Counter (Mirror)
$C0000E	H/V Counter (Mirror)
$C00011	SN76489 PSG
$C00013	SN76489 PSG (Mirror)
$C00015	SN76489 PSG (Mirror)
$C00017	SN76489 PSG (Mirror)

In most occasions, the only parts of the VDP you'll be interested in are the control and data ports, as well as the PSG. The control and data ports are word-wide, but they are mirrored to allow for more efficient long-writes, which lets you program two registers in one instruction, write more art per instruction, and so on, The H/V counter I'm not sure on - I however do know it will tell you the position of the cathode ray inside your TV, or what pixel the VDP is currently drawing. Lastly, you can access the PSG chip. The reason for this being in the VDP address space is that the PSG is actually integrated into the VDP! If you look at the traces on your MD motherboard, you can see that one pin leads to the audio mixing circuit.

VDP Registers

The VDP has 25 registers, of which you can program 24 through code. Some registers do not seem to do anything and are not documented anywhere, but that doesn't mean you shouldn't be afraid to try. The last register isn't a register that is written, but you read back the VDP control to a CPU register or work RAM, you can get various information about the current state of the VDP. Many registers are also programmed as bitfields - meaning you should be able to set individual bits, and then write the final hex number to the VDP control port.

All register values are written to the control port as a word - the first byte being the register number added to $80, and the second byte being the value.

In the tables below, any bits shown as 0 will always be 0, and any values shown as 1 will always be 1. Bits that change something have a letter assigned to them that is explained below the table.

Register 00 - Mode Register 01
128	64	32	16	8	4	2	1
0	0	0	IE1	0	1	HV	0

The state of the bit IE1 decides whether the VDP will generate a horizontal interrupt for every nth scanline, or not. This is a level 4 interrupt for the M68k. A 1 means it is enabled, while 0 means it is disabled. The state of HV lets you 'latch' the contents of the HV counter. If it is set to 1, the VDP will stop modifying the counter so you can read it and calculate things, while when set to 0, the VDP will actively update the counter.

Register 01 - Mode Register 02
128	64	32	16	8	4	2	1
0	DE	IE0	X	Y	1	0	0

DE decides if the display is enabled (1) or disabled (0). This is useful to perform quick art loading. IE0 enables the vertical blank interrupt, or VBI. This is a Level 6 interrupt to the M68k. X allows DMA to be performed when set, while it disables any sort of DMA when it is not set. Y sets the display mode. When set to 1, 30 cell mode is enabled, which is exclusive to PAL. When set to 0, 28 cell mode is enabled, which is always the case on NTSC.

Register 02 - Plane A Name Table Location
128	64	32	16	8	4	2	1
0	0	X	X	X	0	0	0

XXX is the VRAM location of the name table for Plane A divided by 400h. This means that your Plane A name table has to be located at a VRAM address that's a multiple of 400h.

Register 03 - Window Name Table Location
128	64	32	16	8	4	2	1
0	0	X	X	X	0	0	0

XXX is the VRAM location of the name table for the Window Plane divided by 400h. This means that your Window Plane name table has to be located at a VRAM address that's a multiple of 400h.

Register 04 - Plane B Name Table Location
128	64	32	16	8	4	2	1
0	0	0	0	0	X	X	X

XXX is the VRAM location of the name table for Plane B divided by 2000h. This means that your Plane B name table has to be located at a VRAM address that's a multiple of 2000h.