Difference between revisions of "VDP"

Revision as of 01:25, 6 September 2011

The VDP, also known as Video Display Processor, handles all video output on the Mega Drive. The VDP is often known as the YM7101, which is derived from the Sega Master System VDP for backwards compatibility. The Master System VDP is in turn derived from the Texas Instruments TMS9918A. In most (if not all) Mega Drive models, the VDP is a dedicated large chip on the main motherboard.

It has 64 KB of VRAM, which can be used to store patterns (also known as art) plane and sprite name tables, as well as horizontal scroll data. The benefit of storing name tables and H-Scroll in VRAM is that you can decide where this data is stored, but leaves less room for art. The VDP has 64 bytes of 9-bit RAM to store palettes. This special area of the VDP is known as CRAM, or Colour RAM.

The VDP has the capability of displaying up to 80 sprites on-screen, as well as the A and B planes, and the Window plane. The window plane can be used as a replacement for the A plane in some circumstances. It can also support 64 on-screen colours at any time, as well as scrolling the entire screen or specific parts of it horizontally and vertically. There is also multiple registers that control how the VDP is configured, which are written to the control word as 16-bit words.

Accessing the VDP

To access the VDP, you must use a special area of I/O memory. Below is a map of the VDP's IO memory, starting at $C00000:

In most occasions, the only parts of the VDP you'll be interested in are the control and data ports, as well as the PSG. The control and data ports are word-wide, but they are mirrored to allow for more efficient long-writes, which lets you program two registers in one instruction, write more art per instruction, and so on, The H/V counter I'm not sure on - I however do know it will tell you the position of the cathode ray inside your TV, or what pixel the VDP is currently drawing. Lastly, you can access the PSG chip. The reason for this being in the VDP address space is that the PSG is actually integrated into the VDP! If you look at the traces on your MD motherboard, you can see that one pin leads to the audio mixing circuit.

VDP Registers

The VDP has 25 registers, of which you can program 24 through code. Some registers do not seem to do anything and are not documented anywhere, but that doesn't mean you shouldn't be afraid to try. The last register isn't a register that is written, but you read back the VDP control to a CPU register or work RAM, you can get various information about the current state of the VDP. Many registers are also programmed as bitfields - meaning you should be able to set individual bits, and then write the final hex number to the VDP control port.

All register values are written to the control port as a word - the first byte being the register number added to $80, and the second byte being the value.

In the tables below, any bits shown as 0 will always be 0, and any values shown as 1 will always be 1. Bits that change something have a letter assigned to them that is explained below the table.

The state of the bit IE1 decides whether the VDP will generate a horizontal interrupt for every nth scanline, or not. This is a level 4 interrupt for the M68k. A 1 means it is enabled, while 0 means it is disabled. The state of HV lets you 'latch' the contents of the HV counter. If it is set to 1, the VDP will stop modifying the counter so you can read it and calculate things, while when set to 0, the VDP will actively update the counter.

DE decides if the display is enabled (1) or disabled (0). This is useful to perform quick art loading. IE0 enables the vertical blank interrupt, or VBI. This is a Level 6 interrupt to the M68k. X allows DMA to be performed when set, while it disables any sort of DMA when it is not set. Y sets the display mode. When set to 1, 30 cell mode is enabled, which is exclusive to PAL. When set to 0, 28 cell mode is enabled, which is always the case on NTSC.

XXX is the VRAM location of the name table for Plane A divided by 400h. This means that your Plane A name table has to be located at a VRAM address that's a multiple of 400h. If you want your plane A name table to be located at C000h in VRAM, divide that by 400h, giving you the result to write to the VDP register, 30h.

XXX is the VRAM location of the name table for the Window Plane divided by 400h. This means that your Window Plane name table has to be located at a VRAM address that's a multiple of 400h. If you want your window plane name table to be located at F000h in VRAM, divide that by 400h, which gives you 3Ch, which is what you'd write to this register.

XXX is the VRAM location of the name table for Plane B divided by 2000h. This means that your Plane B name table has to be located at a VRAM address that's a multiple of 2000h. If you want the plane B name table to be stored at E000h in VRAM, divide that by 2000h, which gives you 07h, which is the value you'd write to this register.

XXXXXXX is the VRAM location of the sprite attribute table divided by 200h. This means that your sprite attribute table has to be located at a VRAM address that's a multiple of 200h. The lower limit of the location multiple means you can squish between unused space for mappings, and so on. Say you want your sprite attribute table to be located at D800h in VRAM, divide this by 200h and write 6Ch to this register.

This is one of these odd unused registers that aren't documented anywhere to my knowledge. Many, if not all games don't touch these registers. Don't hesitate to edit this page if you have info about one of these, though.

XX is the palette line from where the backdrop colour is to be retrieved from, while YYYY is the entry in that palette to use. Do note that the colour you declared as the transparent colour can be displayed. For example, if you want to use colour 2 of palette line 2, you'll write 11h to this register.

This is one of these odd unused registers that aren't documented anywhere to my knowledge. Many, if not all games don't touch these registers. Don't hesitate to edit this page if you have info about one of these, though.

This is one of these odd unused registers that aren't documented anywhere to my knowledge. Many, if not all games don't touch these registers. Don't hesitate to edit this page if you have info about one of these, though.

HHHHHHHH is what scanline you want your horizontal interrupt to be called on. For this to take any effect, make sure you enabled horizontal interrupts in register 0's IE1, and that you are not blocking interrupts on the M68k side.

IE2 controls external interrupts that are raised by the TH pin on one of the three IO ports. This is how almost all light guns function. When the trigger is depressed, they pull TH high which causes the game's external interrupt routine to run. This is a Level 2 interrupt on the M68k side. VS controls vertical scrolling. When set to 0, the entire screen is scrolled by one longword in VSRAM. When set to 1, every word in VSRAM vertically scrolls two cells, or tiles of art. HS1 and HS2 both control horizontal scrolling. When set to 00, the entire screen is scrolled at once by one longword in the horizontal scroll table. Setting 01 is prohibited, and may cause undefined behaviour. When set to 10, every long scrolls 8 pixels, and when set to 11, every longword scrolls one scanline.

RS0 and RS1 should be set to the same value, seeing as they control the same thing. When set to 0, the VDP is using horizontal 32 tile mode. When set to 1, the VDP will use a 40 tile wide display. SHI enables shadow/highlight, a special mode to allow for more colours on-screen when set. LSM1 and LSM0 control interlace settings: 00 sets no interlace, 01 enables interlace, 10 is prohibited, and 11 interlaces at double resolution. Sonic 2 and some other games use the latter interlace mode for their dual-player split screen.

XXXXXX controls where the HScroll data, if at all, is stored. This location has to be a multiple of 400h. For example, if your HScroll data is located at DC00h, you will divide that by 400h to get 37h.

This is one of these odd unused registers that aren't documented anywhere to my knowledge. Many, if not all games don't touch these registers. Don't hesitate to edit this page if you have info about one of these, though.

XXXXXXXX sets the 8-bit value to add after a VRAM access. This is incredibly useful for writing art to the VDP control port, as you can write a word, and the VDP will automagically increase the VRAM pointer for you. Many games set this to 2.

XX sets the size of the vertical size of both the A and B planes. When set to 00, you will get a 32 tile vertical size, 01 sets 64 tile vertical, and 11 sets 128 vertical tile size. Setting 10 is prohibited and may cause undefined behaviour. YY sets the size of the horizontal size of both the A and B planes. When set to 00, you will get a 32 tile horizontal size, 01 sets 64 tile horizontal, and 11 sets 128 horizontal tile size. Setting 10 is prohibited and may cause undefined behaviour.

It is important to know that a name table can never exceed 8192 bytes. While a 64x64 or 128x32 name table is valid, a 128x128 or 64x128 name table is not valid.

D sets the direction in which to move the window plane horizontally - 0 means to the left, while 1 means to the right. XXXXX sets how many cells to move the window plane horizontally in the direction specified by D.

D sets the direction in which to move the window plane vertically - 0 means up, while 1 means down. XXXXX sets how many cells to move the window plane vertically. in the direction specified by D.

An important feature to know about the window plane is that it masks plane A, even transparent pixels. This makes it unsuitable for use in many circumstances, but some games use it as a HUD.

XXXXXXXX is the low byte of the DMA length. YYYYYYYY is the high byte of the DMA length.

If the DMA length is set to 0, the VDP will treat it as FFFFh, which will cause lots of issues.

XXXXXXXX is the low byte of the DMA source address. YYYYYYYY is the middle byte of the DMA source address. ZZZZZZZZ is the high byte of the DMA source address.