|Fast Facts on the Mega CD|
Made by: Sega
Initially released in late 1991, the Mega-CD expanded the capabilities of the Mega Drive by adding a CD drive and several additional chips, which allowed for the use of Audio CDs and CD+G discs as well as specially-designed games primarily distributed on CD. These additions served as an attempt to gain an upper hand on the oncoming Super Nintendo Entertainment System, as well as compete with NEC's PC Engine CD (TurboGraphx-16 CD in the US), but ultimately failed to gain leverage over either.
Two models of the Mega-CD and several variants were manufactured during the peripheral's lifetime.
The Mega-CD provided a number of enhancements to the Mega Drive's capabilities, including an additional Motorola 68000 processor for managing all the components on the Mega-CD side, an ASIC that added various scaling and rotation capabilities, a PCM chip that provides eight additional PCM channels, 512KB of Program RAM, 256KB of Word RAM that can be shared between the Mega Drive and Mega CD.
At the centre of the Mega CD's design lies a 1x speed CD drive that allowed for listening to Audio CDs or viewing CD+G discs, as well as the ability to play games specially designed to run from CD. Also introduced was BRAM, which allowed games for the Mega-CD to save game progress and other information in one central place.
All of the extra hardware that the Mega CD provides could be taken advantage of using either the cart boot mode (Mode 1) or the CD boot mode (Mode 2), allowing developers two methods to utilize these hardware additions.
Through the production lifespan, the Mega-CD had two distinctively different models, as well as a few notable variants. The Model 1 Mega-CD generally carries BIOS revisions in the v1 range. Its form factor was such that it sat underneath the Model 1 Mega Drive as an extension of the base, fitting the Mega Drive's form factor in all but height, and used a tray-loading CD drive. The Model 2 Mega-CD was released later in the Mega Drive's production life, and was designed with the Model 2 Mega Drive's design in mind. Scrapping the undercarriage design of the Model 1 Mega-CD, the design instead seats the CD drive to the side of the Mega Drive and removes the tray in lieu of a cover. The BIOS software also generally carries a revision in the v2 range. Both models have a stereo out and require a separate power supply from the Mega Drive.
There exists a very uncommon, but official variant manufactured by Sega that was distributed under the name of the Sega Multi-Mega (CDX in North America). This variant provides a combined Mega Drive and Mega-CD in the form factor of a portable CD player. Limited amounts of the Multi-Mega were made, and the system runs off of a single power source. The console uses a single revision of the BIOS (due to its very limited production run) and retains the ability to use a 32x, despite some of the manuals for the console stating otherwise.
The Sega CD has several registers, starting at $A12000 that can control the Sega CD's operation from the Main CPU (Mega Drive) side:
Sub CPU Reset/Halt
- IEN: When set, allows Level 2 interrupt to occur on Sub-CPU.
- INT2 Causes Level 2 interrupt. Set to 1 - it will become 0 when interrupt is processed.
- REQ Request the bus. Set to 1 and read until it is 1 before accessing the Program RAM.
- RST Resets the CPU - set to 0 to reset, 1 to run.
- WP7 to WP0 Allows write protecting of program RAM in $100 increments, starting at $0.
- BK1 to BK0 Sets the current 128 KB bank of Program RAM visible to the main CPU
- MODE When set, the Word RAM is accessible as two 1 MBit banks, or one single 2 MBit bank when clear.
- DMNA In 2 MBit mode, this will swap the RAM to the Sub CPU when set, or the Main CPU when clear. In 1 MBit mode, it will swap the two banks of memory between both CPUs - read and see if it is 0, which indicates completion.
- RET In 2 MBit mode, this bit returns the memory to the Main CPU when set, and Sub CPU when clear. In 1 MBit mode, it will transfer the first bank to the Main CPU, and the second to the Sub CPU when cleared, and vice versa when set.
Horizontal Interrupt Vector
|Address High||Address Low|
The low 16 bits of the address in Main RAM that contains the Horizontal Interrupt handler.
- TD11 to TD0: Each tick of the timer is 30.72µs - once the counter reaches 4095, it will overflow to 0.
|CFM7 to CFM0||CFM7 to CFS0|
- CFM7 to CFM0: 8 bits of memory that can be read by the Sub CPU, and written only by the Main CPU.
- CFM7 to CFS0: 8 bits of memory that can be read by the Main CPU, and written only by the Sub CPU.
Main CPU to Sub CPU
There is 16 bytes of memory, starting at $A12010 that can be written only by the Main CPU, but also read by the Sub CPU.
Sub CPU to Main CPU
There is 16 bytes of memory, starting at $A12020 that can be written only by the Sub CPU, but also read by the Main CPU.