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The 315-5309 in a VA3 Mega Drive.

The 315-5309 is one of the two IO chips that can be found on early (usually pre-TMSS) Mega Drive models. It handles the version register, regions (part of the version register) as well as the three IO ports present on the Mega Drive.


The 315-5309 is a memory mapped peripheral mapped into memory starting at $A10000. Each address described below allows access to a specific 'register' of the chip that can control various aspects.

Start End
$A10001 $A10001 Version register
$A10003 $A10003 Data 1
$A10005 $A10005 Data 2
$A10007 $A10007 Data 3
$A10009 $A10009 Control 1
$A1000B $A1000B Control 2
$A1000D $A1000D Control 3
$A1000F $A1000F TxD 1
$A10011 $A10011 RxD 1
$A10013 $A10013 Serial Control 1
$A10015 $A10015 TxD 2
$A10017 $A10017 RxD 2
$A10019 $A10019 Serial Control 2
$A1001B $A1001B TxD 3
$A1001D $A1001D RxD 3
$A1001F $A1001F Serial Control 3

Version Register

The Version register allows programs to check both the region (Overseas or Domestic) and the video mode - NTSC or PAL. These two settings are actually affected by JP 1 through 4, not by the actual frequency. It also indicates the presence of the disk drive (intended originally for the unreleased FDD, but also indicates presence of the Sega CD) and the version of the hardware - this is used to detect if the TMSS needs "SEGA" written to $A14000. The register is laid out as follows:

Version Register
128 64 32 16 8 4 2 1
  • REG: When set, the Mega Drive is an Overseas model. When clear, it is a Domestic model. This is controlled by JP4 (overseas) and JP1 (domestic)
  • PAL: When set, the Mega Drive is a PAL model. When clear, it is an NTSC model. This is controlled by JP3 and JP2.
  • DISK: Indicates presence of an FDD, or Sega CD when cleared.
  • V3 to V0: Indicates the hardware revision. Revisions 1 and above have TMSS.

Data Register

The data register allows setting/reading of the various control port bits. For example, setting bit 6 will pull /TH high, which is used to read out controllers. See this article for more info. The register's bits are laid out like so:

Data Register
128 64 32 16 8 4 2 1
  • PD7: Unused. Should be set as 0.
  • PD7: /TH pin. Used for the multiplexer inside the controller.
  • PD5: Start or C
  • PD4: A or B
  • PD3: Right
  • PD2: Left
  • PD1: Down
  • PD0: Up

Control Register

The control register is used to specify the if a pin on the controller port connector is an input or an output, and if an externally induced /TH change will cause an interrupt.

Control Register Format
128 64 32 16 8 4 2 1
  • INT: If set, an external /TH change can create a level 2 interrupt, if it is not masked by the VDP's registers or the Motorola 68000's interrupt mask.
  • PC6 to PC0: The input/output states for each of those pins - When set, the pin operates in output mode, or as an input if clear.


The IO controller can put each of the three IO ports on the Mega Drive into 'serial mode,' In this mode, the controller will shift each bit of a byte out to a pin on the controller at up to 4800 baud. It can also handle turning a received data back into a byte and then causing an interrupt, if desired. Data is read through the RxD and written through TxD registers for each port.

Serial Control

Each port has a serial control register, which dictates how the serial mode will work:

Serial Control Format
128 64 32 16 8 4 2 1
  • BPS1 and BPS0: Define the baud rate used by the serial mode, in a range between 4800 down to 300 baud. See table below.
  • SIN: When set, the pin on the control port used for A or B is used as the serial input pin.
  • SOUT: When set, the pin on the control port used for Start or C is used as the serial output pin.
  • RINT: When set, a level 2 interrupt is created when data arrives and is already decoded.
  • RRDY: Set when the receive component of the chip is ready.
  • TFUL: Set when the transmit buffer is filled. Always wait for this bit to be 0 before writing a new value.

Baud Rates

Four different baud rates between 4800 and 300 baud can be selected using the BPS1 and BPS0 bits:

BPS0 BPS1 Resulting Baud Rate
0 0 4800 bps
0 1 2800 bps
1 0 1200 bps
1 1 300 bps

The I/O controller outputs in a format very similar to RS-232: To start, it will insert a start bit, a transition from high to low, transmit data bit by bit, and then transmit the end bit, going from low to high again.


The 315-5309 is a 80 pin TQFP package on the main board of pre-TMSS Model 1 Mega Drives near the two controller ports.

315-5309 pinout.png