Difference between revisions of "RF5C164"

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m (Tristan Seifert moved page RF5C68A to RF5C164: The RF5C68A is very closely related to the chip in the Mega CD, but a RF5C164 was used in it.)
(Added partial register map)
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The '''RF5C68A''' is a PCM playback chip that is capable of playing eight simultaneous channels.
+
The '''RF5C68A''' is a PCM playback chip that is capable of playing eight simultaneous channels. Samples are stored in sign-magnitude format instead of Two's Compliment, but conversion can be achieved by flipping the most significant bit of the sample.
 +
 
 +
Note that this article is written in the context of the [[Mega CD]] — while the information still applies to this chip in other systems, absolute addresses may not be the same as they are elsewhere. Please use caution when using this reference.
 +
 
 +
== Sample Storage ==
 +
In order to hold samples, the RF5C164 can connect to up to 64 KB of Mask ROM, PSRAM, or SRAM. In the case of RAM, this memory is accessible to the system the RF5C164 is connected to through windows of 4 KB each. This window is located at <code>$1000</code> and goes up to <code>$1FFF.</code> To write to all of the memory, a banking mechanism is instituted in the chip that can change which of the 16 banks is currently accessible through this window. The active window can be changed through the [[#Control Register|control register.]]
 +
 
 +
== Registers ==
 +
To control various aspects of the sample playback, including sample rate, panning, volume, address, as well as loop point, the RF5C164 has several registers through which these settings can be controlled. All registers except the sample start address are banked and will change depending on what channel is selected through the [[#Control Register|control register.]]
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 +
=== Register Map ===
 +
{| class="wikitable" width="320px"
 +
|-
 +
! Address
 +
! Function
 +
|-
 +
| <code>$0000</code>
 +
| Envelope
 +
|-
 +
| <code>$0001</code>
 +
| Pan
 +
|-
 +
| <code>$0002</code>
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| Address increment low
 +
|-
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| <code>$0003</code>
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| Address increment high
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|-
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| <code>$0004</code>
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| Loop start address low
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|-
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| <code>$0005</code>
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| Loop start address high
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|-
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| <code>$0006</code>
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| Sample start address (high only)
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|-
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| <code>$0007</code>
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|  [[#Control Register|Control Register]]
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|-
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| <code>$0008</code>
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| Channel on/off
 +
|}
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 +
=== Control Register ===
 +
{| class="wikitable" width="320px"
 +
|-
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! colspan="8" | <code>$0007</code> - Control Register
 +
|-
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! 7
 +
! 6
 +
! 5
 +
! 4
 +
! 3
 +
! 2
 +
! 1
 +
! 0
 +
|-
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| align="center" rowspan="2" | SE
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| align="center" rowspan="2" | MOD
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| align="center" rowspan="2" | 0
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| align="center" rowspan="2" | 0
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| align="center" | WB3
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| align="center" | WB2
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| align="center" | WB1
 +
| align="center" | WB0
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|-
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| align="center" | 0
 +
| align="center" | CB2
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| align="center" | CB1
 +
| align="center" | CB0
 +
|}
 +
 
 +
* '''SE:''' When set, the chip begins producing sound, disabling all of the eight channels when cleared.
 +
* '''MOD:''' Controls the selection of what the lower four bits of the register do. When set to one, CB2-CB0 are read.
 +
 
 +
==== MOD = 1 ====
 +
* '''CB2-CB0:''' Channel to access through channel control registers (<code>$0000</code> to <code>$0006</code>)
 +
 
 +
==== MOD = 0 ====
 +
* '''WB3-WB0:''' Bank to access through the PCM memory window.
 +
 
 +
The value contained in these bits is multiplied by <code>$1000</code> and added to the lower 12 bits of the address when the PCM memory window is accessed.
 +
 
 +
=== Envelope ===
 +
{| class="wikitable" width="320px"
 +
|-
 +
! colspan="8" | <code>$0000</code> - Envelope
 +
|-
 +
! 7
 +
! 6
 +
! 5
 +
! 4
 +
! 3
 +
! 2
 +
! 1
 +
! 0
 +
|-
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| align="center" colspan="8" | ENV
 +
|}
 +
* '''ENV:''' This value is multiplied with the low 7 bits of the sample data to produce an unsigned 16-bit value.
 +
 
 +
=== Pan ===
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{| class="wikitable" width="320px"
 +
|-
 +
! colspan="8" | <code>$0001</code> - Pan
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|-
 +
! 7
 +
! 6
 +
! 5
 +
! 4
 +
! 3
 +
! 2
 +
! 1
 +
! 0
 +
|-
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| align="center" colspan="4" | R
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| align="center" colspan="4" | L
 +
|}
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* '''R''' and '''L:''' 4-bit values that are multiplied by the unsigned 16-bit value created after envelope calculation, resulting in a 19-bit unsigned value.
 +
 
 +
=== Address increment ===
 +
This group of registers specifies the amount to increment the sample address by each sound cycle.
 +
 
 +
{| class="wikitable" width="320px"
 +
|-
 +
! colspan="8" | <code>$0002</code> - Address Increment Low
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!
 +
! colspan="8" | <code>$0008</code> - Address Increment High
 +
|-
 +
! 7
 +
! 6
 +
! 5
 +
! 4
 +
! 3
 +
! 2
 +
! 1
 +
! 0
 +
!
 +
! 7
 +
! 6
 +
! 5
 +
! 4
 +
! 3
 +
! 2
 +
! 1
 +
! 0
 +
|-
 +
| align="center" colspan="8" | FDL
 +
|
 +
| align="center" colspan="8" | FDH
 +
|}
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 +
When a certain bit in each register is set, a value associated with that bit is added to the address each sample cycle. These values are:
 +
{| class="wikitable" width="320px"
 +
|-
 +
! Bit
 +
! FDL Increment
 +
! FDH Increment
 +
|-
 +
| 7
 +
| 2<sup>-4</sup>
 +
| 2<sup>4</sup>
 +
|-
 +
| 6
 +
| 2<sup>-5</sup>
 +
| 2<sup>3</sup>
 +
|-
 +
| 5
 +
| 2<sup>-6</sup>
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| 2<sup>2</sup>
 +
|-
 +
| 4
 +
| 2<sup>-7</sup>
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| 2<sup>1</sup>
 +
|-
 +
| 3
 +
| 2<sup>-8</sup>
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| 2<sup>0</sup>
 +
|-
 +
| 2
 +
| 2<sup>-9</sup>
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| 2<sup>-1</sup>
 +
|-
 +
| 1
 +
| 2<sup>-10</sup>
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| 2<sup>-2</sup>
 +
|-
 +
| 0
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| 2<sup>-11</sup>
 +
| 2<sup>-3</sup>
 +
|}
  
 
[[Category:Hardware]]
 
[[Category:Hardware]]
 
[[Category:MegaCD]]
 
[[Category:MegaCD]]

Revision as of 19:29, 20 July 2013

This short article is in need of work. You can help us by adding to it.


The RF5C68A is a PCM playback chip that is capable of playing eight simultaneous channels. Samples are stored in sign-magnitude format instead of Two's Compliment, but conversion can be achieved by flipping the most significant bit of the sample.

Note that this article is written in the context of the Mega CD — while the information still applies to this chip in other systems, absolute addresses may not be the same as they are elsewhere. Please use caution when using this reference.

Sample Storage

In order to hold samples, the RF5C164 can connect to up to 64 KB of Mask ROM, PSRAM, or SRAM. In the case of RAM, this memory is accessible to the system the RF5C164 is connected to through windows of 4 KB each. This window is located at $1000 and goes up to $1FFF. To write to all of the memory, a banking mechanism is instituted in the chip that can change which of the 16 banks is currently accessible through this window. The active window can be changed through the control register.

Registers

To control various aspects of the sample playback, including sample rate, panning, volume, address, as well as loop point, the RF5C164 has several registers through which these settings can be controlled. All registers except the sample start address are banked and will change depending on what channel is selected through the control register.

Register Map

Address Function
$0000 Envelope
$0001 Pan
$0002 Address increment low
$0003 Address increment high
$0004 Loop start address low
$0005 Loop start address high
$0006 Sample start address (high only)
$0007 Control Register
$0008 Channel on/off

Control Register

$0007 - Control Register
7 6 5 4 3 2 1 0
SE MOD 0 0 WB3 WB2 WB1 WB0
0 CB2 CB1 CB0
  • SE: When set, the chip begins producing sound, disabling all of the eight channels when cleared.
  • MOD: Controls the selection of what the lower four bits of the register do. When set to one, CB2-CB0 are read.

MOD = 1

  • CB2-CB0: Channel to access through channel control registers ($0000 to $0006)

MOD = 0

  • WB3-WB0: Bank to access through the PCM memory window.

The value contained in these bits is multiplied by $1000 and added to the lower 12 bits of the address when the PCM memory window is accessed.

Envelope

$0000 - Envelope
7 6 5 4 3 2 1 0
ENV
  • ENV: This value is multiplied with the low 7 bits of the sample data to produce an unsigned 16-bit value.

Pan

$0001 - Pan
7 6 5 4 3 2 1 0
R L
  • R and L: 4-bit values that are multiplied by the unsigned 16-bit value created after envelope calculation, resulting in a 19-bit unsigned value.

Address increment

This group of registers specifies the amount to increment the sample address by each sound cycle.

$0002 - Address Increment Low $0008 - Address Increment High
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
FDL FDH

When a certain bit in each register is set, a value associated with that bit is added to the address each sample cycle. These values are:

Bit FDL Increment FDH Increment
7 2-4 24
6 2-5 23
5 2-6 22
4 2-7 21
3 2-8 20
2 2-9 2-1
1 2-10 2-2
0 2-11 2-3
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