68k Instruction Reference
This page documents all Motorola 68000 instructions, as well as their execution times. When instruction timings are shown, they are usually in the format of x(r/w), where x is the total number of processor cycles required for the instruction, and r/w is the total read and write cycles required for the instruction.
Instruction timings include instruction fetches, operand reads, as well as operand writes.
Contents
- 1 Address Calculation Times
- 2 Move Instruction Execution Times
- 3 Standard Instruction Execution Times
- 4 Immediate Instruction Execution Times
- 5 Single Operand Instruction Execution Times
- 6 Rotate Instruction Execution Times
- 7 Bit Manipulation Instruction Execution Times
- 8 Conditional Instruction Execution Times
- 9 JMP, JSR, LEA, PEA and MOVEM Instruction Execution Times
- 10 Multi-Precision Instruction Execution Times
- 11 Miscellaneous Instruction Execution Times
- 12 Exception Processing Execution Times
Address Calculation Times
It is important to remember that most instructions alter some form of memory, and thus, must calculate the address that will be accessed, which usually incurs extra processor cycles. The two columns "Byte/Word" and "Long" contain a number followed by two numbers in parenthesis. The number outside the parenthesis indicates the total number of processor cycles required, while the two numbers inside the parenthesis indicate the number of read and write cycles are required.
Timings include fetching of extension words, address computation, as well as fetching of memory operands.
Addressing Mode | Byte/Word | Long | |
---|---|---|---|
Register | |||
Dn | Data Register Direct | 0(0/0) | 0(0/0) |
An | Address Register Direct | 0(0/0) | 0(0/0) |
Memory | |||
(An) | Address Register Indirect | 4(1/0) | 8(2/0) |
(An)+ | Address Register Indirect with post-increment | 4(1/0) | 8(2/0) |
-(An) | Address Register Indirect with pre-decrement | 6(1/0) | 10(2/0) |
d(An) | Address Register Indirect with displacement | 8(2/0) | 12(3/0) |
d(An, ix) | Address Register Indirect with index | 10(2/0) | 14(3/0) |
#xxx.W | Absolute Short | 8(2/0) | 12(3/0) |
#xxx.L | Absolute Long | 12(3/0) | 16(4/0) |
d(PC) | Program Counter with displacement | 8(2/0) | 12(3/0) |
d(PC, ix) | Program Counter with index | 10(2/0) | 14(3/0) |
#xxx | Immediate | 4(1/0) | 8(2/0) |
Move Instruction Execution Times
Note: The size of the index register (ix) does not affect the instruction execution time.
Byte and Word
Dn | An | (An) | (An)+ | -(An) | d(An) | d(An, ix) | #xxx.W | #xxx.L | |
---|---|---|---|---|---|---|---|---|---|
Dn | 4(1/0) | 4(1/0) | 8(1/1) | 8(1/1) | 8(1/1) | 12(2/1) | 14(2/1) | 12(2/1) | 16(3/1) |
An | 4(1/0) | 4(1/0) | 8(1/1) | 8(1/1) | 8(1/1) | 12(2/1) | 14(2/1) | 12(2/1) | 16(3/1) |
(An) | 8(2/0) | 8(2/0) | 12(2/1) | 12(2/1) | 12(2/1) | 16(3/1) | 18(3/1) | 16(3/1) | 20(4/1) |
(An)+ | 8(2/0) | 8(2/0) | 12(2/1) | 12(2/1) | 12(2/1) | 16(3/1) | 18(3/1) | 16(3/1) | 20(4/1) |
-(An) | 10(2/0) | 10(2/0) | 14(2/1) | 14(2/1) | 14(2/1) | 18(3/1) | 20(4/1) | 18(3/1) | 22(4/1) |
d(An) | 12(3/0) | 12(3/0) | 16(3/1) | 16(3/1) | 16(3/1) | 20(4/1) | 22(4/1) | 20(4/1) | 24(5/1) |
d(An, ix) | 14(3/0) | 14(3/0) | 18(3/1) | 18(3/1) | 18(3/1) | 22(4/1) | 24(4/1) | 22(4/1) | 26(5/1) |
#xxx.W | 12(3/0) | 12(3/0) | 16(3/1) | 16(3/1) | 16(3/1) | 20(4/1) | 22(4/1) | 20(4/1) | 24(5/1) |
#xxx.L | 16(4/0) | 16(4/0) | 20(4/1) | 20(4/1) | 20(4/1) | 24(5/1) | 26(5/1) | 24(5/1) | 28(6/1) |
d(PC) | 12(3/0) | 12(3/0) | 16(3/1) | 16(3/1) | 16(3/1) | 20(4/1) | 22(4/1) | 20(4/1) | 24(5/1) |
d(PC, ix) | 14(3/0) | 14(3/0) | 18(3/1) | 18(3/1) | 18(3/1) | 22(4/1) | 24(4/1) | 22(4/1) | 26(5/1) |
#xxx | 8(2/0) | 8(2/0) | 12(2/1) | 12(2/1) | 12(2/1) | 16(3/1) | 18(3/1) | 16(3/1) | 20(4/1) |
Longword
Dn | An | (An) | (An)+ | -(An) | d(An) | d(An, ix) | #xxx.W | #xxx.L | |
---|---|---|---|---|---|---|---|---|---|
Dn | 4(1/0) | 4(1/0) | 12(1/2) | 12(1/2) | 12(1/2) | 16(2/2) | 18(2/2) | 16(2/2) | 20(3/2) |
An | 4(1/0) | 4(1/0) | 12(1/2) | 12(1/2) | 12(1/2) | 16(2/2) | 18(2/2) | 16(2/2) | 20(3/2) |
(An) | 12(3/0) | 12(3/0) | 20(3/2) | 20(3/2) | 20(3/2) | 24(4/2) | 26(4/2) | 24(4/2) | 28(5/2) |
(An)+ | 12(3/0) | 12(3/0) | 20(3/2) | 20(3/2) | 20(3/2) | 24(4/2) | 26(4/2) | 24(4/2) | 28(5/2) |
-(An) | 14(3/0) | 14(3/0) | 22(3/2) | 22(3/2) | 22(3/2) | 26(4/2) | 28(4/2) | 26(4/2) | 30(5/2) |
d(An) | 16(4/0) | 16(4/0) | 24(4/2) | 24(4/2) | 24(4/2) | 28(5/2) | 30(5/2) | 28(5/2) | 32(6/2) |
d(An, ix) | 18(4/0) | 18(4/0) | 26(4/2) | 26(4/2) | 26(4/2) | 30(5/2) | 32(5/2) | 30(5/2) | 34(6/2) |
#xxx.W | 16(4/0) | 16(4/0) | 24(4/2) | 24(4/2) | 24(4/2) | 28(5/2) | 30(5/2) | 28(5/2) | 32(6/2) |
#xxx.L | 20(5/0) | 20(5/0) | 28(5/2) | 28(5/2) | 28(5/2) | 32(6/2) | 34(6/2) | 32(6/2) | 36(7/2) |
d(PC) | 16(4/0) | 16(4/0) | 24(4/2) | 24(4/2) | 24(4/2) | 28(5/2) | 30(5/2) | 28(5/2) | 32(5/2) |
d(PC, ix) | 18(4/0) | 18(4/0) | 26(4/2) | 26(4/2) | 26(4/2) | 30(5/2) | 32(5/2) | 30(5/2) | 34(6/2) |
#xxx | 12(3/0) | 12(3/0) | 20(3/2) | 20(3/2) | 20(3/2) | 24(4/2) | 26(4/2) | 24(4/2) | 28(5/2) |
Standard Instruction Execution Times
The number of processor clocks shown in this table indicate the time required to perform the operations, store the results, and to read the next instruction. When indicated by a +, the effective address calculation time must be added to the time required for the instruction itself.
Headings in the table have the following meanings:
- An = Address register operand
- Dn = Data register operand
- ea = Operand specified by effective address
- M = Memory operand
Size | op<ea>, An^ | op<ea>, Dn | op Dn, <M> | |
---|---|---|---|---|
ADD | B, W | 8(1/0)+ | 4(1/0)+ | 8(1/1)+ |
L | 6(1/0)+** | 6(1/0)+** | 12(1/2)+ | |
AND | B, W | - | 4(1/0)+ | 8(1/1)+ |
L | - | 6(1/0)+** | 12(1/2)+ | |
CMP | B, W | 6(1/0)+ | 4(1/0)+ | - |
L | 6(1/0)+ | 6(1/0)+ | - | |
DIVS | - | - | 158(1/0)+* | - |
DIVU | - | - | 140(1/0)+* | - |
EOR | B, W | - | 4(1/0)*** | 8(1/1)+ |
L | - | 8(1/0)*** | 12(1/2)+ | |
MULS | - | - | 70(1/0)+* | - |
MULU | - | - | 70(1/0)+* | - |
OR | B, W | - | 4(1/0)+ | 8(1/1)+ |
L | - | 6(1/0)+** | 12(1/2)+ | |
SUB | B, W | 8(1/0)+ | 4(1/0)+ | 8(1/1)+ |
L | 6(1/0)+** | 6(1/0)+** | 12(1/2)+ |
- +: Add effective address calculation time to specified instruction execution time.
- ^: Word or long only
- *: Maximum value (worst case)
- **: Base time of six clocks is increased to eight if the effective address mode is register direct or immediate (effective address calculation time should also be added)
- ***: The only available effective address mode is data register direct
DIVS and DIVU
The divide algorithm that is implemented in the 68000 gives a less than 10% time difference between best and worst case timings.
MULS and MULU
The multiplication algorithm implemented requires 38+2n
clocks, where n is defined as:
- MULU: n = the number of ones in the <ea>
- MULS: n = concatanate the <ea> with a zero as the LSB; n is the resultant number of 10 or 01 patterns in the 17-bit source; i.e., worst case happens when the source is
$5555
Immediate Instruction Execution Times
The number of processor clocks shown in this table indicate the time required to fetch the immediate operands, perform the operations, store the results, and to read the next instruction. When indicated by a +, the effective address calculation time must be added to the time required for the instruction itself.
Size | op #, Dn | op #, An | op #, <M> | |
---|---|---|---|---|
ADDI | B, W | 8(2/0) | - | 12(2/1)+ |
L | 16(3/0) | - | 20(3/2)+ | |
ADDQ | B, W | 4(1/0) | 8(1/0)* | 8(1/1)+ |
L | 8(1/0) | 8(1/0) | 12(1/2)+ | |
ANDI | B, W | 8(2/0) | - | 12(2/1)+ |
L | 16(3/0) | - | 20(3/1)+ | |
CMPI | B, W | 8(2/0) | - | 8(2/0)+ |
L | 14(3/0) | - | 12(3/0)+ | |
EORI | B, W | 8(2/0) | - | 12(2/1)+ |
L | 16(3/0) | - | 20(3/2)+ | |
MOVEQ | L | 4(1/0) | - | - |
ORI | B, W | 8(2/0) | - | 12(2/1)+ |
L | 16(3/0) | - | 20(3/2)+ | |
SUBI | B, W | 8(2/0) | - | 12(2/1)+ |
L | 16(3/0) | - | 20(3/2)+ | |
SUBQ | B, W | 4(1/0) | 8(1/0)* | 8(1/1)+ |
L | 8(1/0) | 8(1/0) | 12(1/2)+ |
- +: Add effective address calculation time to specified instruction execution time.
- ^: Word only
Single Operand Instruction Execution Times
The number of processor clocks shown in this table indicate the time required for the single operand instructions. When indicated by a +, the effective address calculation time must be added to the time required for the instruction itself.
Size | Register | Memory | |
---|---|---|---|
CLR | B, W | 4(1/0) | 8(1/1)+ |
L | 6(1/0) | 12(1/2)+ | |
NBCD | B | 6(1/0) | 8(1/1)+ |
NEG | B, W | 4(1/0) | 8(1/1)+ |
L | 6(1/0) | 12(1/2)+ | |
NEGX | B, W | 4(1/0) | 8(1/1)+ |
L | 6(1/0) | 12(1/2)+ | |
NOT | B, W | 4(1/0) | 8(1/1)+ |
L | 6(1/0) | 12(1/2)+ | |
SCC | B, false | 4(1/0) | 8(1/1)+ |
B, true | 6(1/0) | 8(1/1)+ | |
TAS | B | 4(1/0) | 10(1/1)+ |
TST | B, W | 4(1/0) | 4(1/0)+ |
L | 4(1/0) | 4(1/0)+ |
- +: Add effective address calculation time to specified instruction execution time.
Rotate Instruction Execution Times
The number of processor clocks shown in this table indicate the time required for the shift and rotate instructions. When indicated by a +, the effective address calculation time must be added to the time required for the instruction itself.
Size | Register | Memory | |
---|---|---|---|
ASR, ASL | B, W | 6+2n(1/0) | 8(1/1)+ |
L | 8+2n(1/0) | - | |
LSR, LSL | B, W | 6+2n(1/0) | 8(1/1)+ |
L | 8+2n(1/0) | - | |
ROR, ROL | B, W | 6+2n(1/0) | 8(1/1)+ |
L | 8+2n(1/0) | - | |
ROXR, ROXL | B, W | 6+2n(1/0) | 8(1/1)+ |
L | 8+2n(1/0) | - |
- +: Add effective address calculation time to specified instruction execution time.
-
n
is the shift or rotate count
Bit Manipulation Instruction Execution Times
The number of processor clocks shown in this table indicate the time required for the bit manipulation instructions. When indicated by a +, the effective address calculation time must be added to the time required for the instruction itself.
In addition to the regular timing, the bit manipulation instructions take different amounts of cycles to execute when the bit value is either dynamically specified in a register, or static, specified as a literal.
Size | Dynamic | Static | |||
---|---|---|---|---|---|
Register | Memory | Register | Memory | ||
BCHG | Byte | - | 8(1/1)+ | - | 12(2/1)+ |
Long | 8(1/0)* | - | 12(2/0)* | - | |
BCLR | Byte | - | 8(1/1)+ | - | 12(2/1)+ |
Long | 10(1/0)* | - | 14(2/0)* | - | |
BSET | Byte | - | 8(1/1)+ | - | 12(2/1)+ |
Long | 8(1/0)* | - | 12(2/0)* | - | |
BTST | Byte | - | 4(1/0)+ | - | 8(2/0)+ |
Long | 6(1/0)* | - | 10(2/0)* | - |
- +: Add effective address calculation time to specified instruction execution time.
- *: Indicates maximum value (worst case)
Conditional Instruction Execution Times
The number of processor clocks shown in this table indicate the time required to execute the conditional instructions. Instructions have different timings depending on if the branch was taken or not taken.
Displacement | Branch Taken | Branch Not Taken | |
---|---|---|---|
Bcc | Byte | 10(2/0) | 8(1/0) |
Word | 10(2/0) | 12(1/0) | |
BRA | Byte | 10(2/0) | - |
Word | 10(2/0) | - | |
BSR | Byte | 18(2/2) | - |
Word | 18(2/2) | - | |
DBcc | CC true | - | 12(2/0) |
CC false | 10(2/0) | 14(3/0) |
|-
|style="font-weight: bold; background: #f2f2f2; text-align: right;"|JMP||-||
JMP, JSR, LEA, PEA and MOVEM Instruction Execution Times
Size | (An) | (An)+ | -(An) | d(An) | d(An, ix) | #xxx.W | #xxx.L | d(PC) | d(PC, ix)* | |
---|---|---|---|---|---|---|---|---|---|---|
JMP | - | 8(2/0) | - | - | 10(2/0) | 14(3/0) | 10(2/0) | 12(3/0) | 10(2/0) | 14(3/0) |
JSR | - | 16(2/2) | - | - | 18(2/2) | 22(2/2) | 18(2/2) | 20(3/2) | 18(2/2) | 22(2/2) |
LEA | - | 4(1/0) | - | - | 8(2/0) | 12(2/0) | 8(2/0) | 12(3/0) | 8(2/0) | 12(2/0) |
PEA | - | 12(1/2) | - | - | 16(2/2) | 20(2/2) | 16(2/2) | 20(3/2) | 16(2/2) | 20(2/2) |
MOVEM | Word | 12+4n | 12+4n | - | 16+4n | 18+4n | 16+4n | 20+4n | 16+4n | 18+4n |
M->R | (3+n/0) | (3+n/0) | - | (4+n/0) | (4+n/0) | (4+n/0) | (5+n/0) | (4+n/0) | (4+n/0) | |
Long | 12+8n | 12+8n | - | 16+8n | 18+8n | 16+8n | 20+8n | 16+8n | 18+8n | |
(3+2n/0) | (3+2n/0) | - | (4+2n/0) | (4+2n/0) | (4+2n/0) | (5+2n/0) | (4+2n/0) | (4+2n/0) | ||
MOVEM | Word | 8+4n | - | 8+4n | 12+4n | 14+4n | 12+4n | 16+4n | - | - |
R->M | (2/n) | - | (2/n) | (3/n) | (3/n) | (3/n) | (4/n) | - | - | |
Long | 8+8n | - | 8+8n | 12+8n | 14+8n | 12+8n | 16+8n | - | - | |
(2/2n) | - | (2/2n) | (3/2n) | (3/2n) | (3/2n) | (4/2n) | - | - |
n
is the number of registers to move.- *: The size of the index register does not affect execution time of the instruction.
Multi-Precision Instruction Execution Times
The number of processor clocks shown in this table indicate the time required to fetch both operands, perform the multi-precision operations, store the results, and to read the next instruction.
Size | op Dn, Dn | op M, M | |
---|---|---|---|
ADDX | B, W | 4(1/0) | 18(3/1) |
L | 8(1/0) | 30(5/2) | |
CMPM | B, W | - | 12(3/0) |
L | - | 20(5/0) | |
SUB | B, W | 4(1/0) | 18(3/1) |
L | 8(1/0) | 30(5/2) | |
ABCD | B | 6(1/0) | 18(3/1) |
SBCD | B | 6(1/0) | 18(3/1) |
Miscellaneous Instruction Execution Times
The number of processor clocks shown in this table indicate the time required for the shift and rotate instructions. When indicated by a +, the effective address calculation time must be added to the time required for the instruction itself.
Size | Register | Memory | |
---|---|---|---|
ANDI to CCR | byte | 20(3/0) | - |
ANDI to SR | word | 20(3/0) | - |
CHK | - | 10(1/0)+ | - |
EORI to CCR | byte | 20(3/0) | - |
EORI to SR | word | 20(3/0) | - |
ORI to CCR | byte | 20(3/0) | - |
ORI to SR | word | 20(3/0) | - |
MOVE from SR | - | 6(1/0) | 8(1/1)+ |
MOVE to CCR | - | 12(1/0) | 12(1/0)+ |
MOVE to SR | - | 12(1/0) | 12(1/0)+ |
EXG | - | 6(1/0) | - |
EXT | word | 4(1/0) | - |
long | 4(1/0) | - | |
LINK | - | 16(2/2) | - |
MOVE from USP | - | 4(1/0) | - |
MOVE to USP | - | 4(1/0) | - |
NOP | - | 4(1/0) | - |
RESET | - | 132(1/0) | - |
RTE | - | 20(5/0) | - |
RTR | - | 20(5/0) | - |
RTS | - | 16(4/0) | - |
STOP | - | 4(0/0) | - |
SWAP | - | 4(1/0) | - |
TRAPV (No Trap) | - | 4(1/0) | - |
UNLK | - | 12(3/0) | - |
- +: Add effective address calculation time to specified instruction execution time.
Move Peripheral Instruction Execution Times
The number of processor clocks shown in this table indicate the time required for the move peripheral instruction.
Size | Register to Memory | Memory to Register | |
---|---|---|---|
MOVEP | Word | 16(2/2) | 16(4/0) |
Long | 24(2/4) | 24(6/0) |
Exception Processing Execution Times
This table indicates the amount of processor cycles required for the processor to process an exception and begin executing it's handler. Clock periods include the time required for all stacking, the vector fetch, as well as the fetch of the first two instruction words of the handler routine.
Exception | Cycles |
---|---|
Address error | 50(4/7) |
Bus error | 50(4/7) |
CHK instruction (trap taken) | 44(5/3) + |
Divide by Zero | 42(5/3) |
illegal instruction | 34(4/3) |
interrupt | 44(5/3) * |
privilege violation | 34(4/3) |
RESET ** |
40(6/0) |
Trace | 34(4/3) |
TRAP instruction | 38(4/3) |
TRAPV instruction (trap taken) | 34(4/3) |
- +: Add effective address calculation time to execution time.
- *: The interrupt acknowledge cycle is assumed to take four clock periods.
- ** indicates the time from when
RESET
andHALT
are first sampled as negated to when instruction execution starts.