Difference between revisions of "68k Instruction Reference"
(Added Single Operand Instruction Execution Times) |
(Added rotate instructions) |
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| ||L||4(1/0)||4(1/0)<sup>+</sup> | | ||L||4(1/0)||4(1/0)<sup>+</sup> | ||
|} | |} | ||
+ | |||
+ | * <sup>+</sup>: Add effective address calculation time to specified instruction execution time. | ||
+ | |||
+ | == Rotate Instruction Execution Times == | ||
+ | The number of processor clocks shown in this table indicate the time required for the shift and rotate instructions. When indicated by a <sup>+</sup>, the effective address calculation time must be added to the time required for the instruction itself. | ||
+ | |||
+ | {| class="wikitable" | ||
+ | ! !!Size!!Register!!Memory | ||
+ | |- | ||
+ | |ASR, ASL||B, W||6+2n(1/0)||8(1/1)<sup>+</sup> | ||
+ | |- | ||
+ | | ||L||8+2n(1/0)||- | ||
+ | |- | ||
+ | |LSR, LSL||B, W||6+2n(1/0)||8(1/1)<sup>+</sup> | ||
+ | |- | ||
+ | | ||L||8+2n(1/0)||- | ||
+ | |- | ||
+ | |ROR, ROL||B, W||6+2n(1/0)||8(1/1)<sup>+</sup> | ||
+ | |- | ||
+ | | ||L||8+2n(1/0)||- | ||
+ | |- | ||
+ | |ROXR, ROXL||B, W||6+2n(1/0)||8(1/1)<sup>+</sup> | ||
+ | |- | ||
+ | | ||L||8+2n(1/0)||- | ||
+ | |} | ||
+ | |||
+ | * <sup>+</sup>: Add effective address calculation time to specified instruction execution time. | ||
+ | * <code>n</code> is the shift or rotate count | ||
[[Category:MegaDrive]] | [[Category:MegaDrive]] | ||
[[Category:Hardware]] | [[Category:Hardware]] |
Revision as of 20:30, 23 June 2013
This page documents all Motorola 68000 instructions, as well as their execution times. When instruction timings are shown, they are usually in the format of x(r/w), where x is the total number of processor cycles required for the instruction, and r/w is the total read and write cycles required for the instruction.
Instruction timings include instruction fetches, operand reads, as well as operand writes.
Contents
Address Calculation Times
It is important to remember that most instructions alter some form of memory, and thus, must calculate the address that will be accessed, which usually incurs extra processor cycles. The two columns "Byte/Word" and "Long" contain a number followed by two numbers in parenthesis. The number outside the parenthesis indicates the total number of processor cycles required, while the two numbers inside the parenthesis indicate the number of read and write cycles are required.
Timings include fetching of extension words, address computation, as well as fetching of memory operands.
Addressing Mode | Byte/Word | Long | |
---|---|---|---|
Register | |||
Dn | Data Register Direct | 0(0/0) | 0(0/0) |
An | Address Register Direct | 0(0/0) | 0(0/0) |
Memory | |||
(An) | Address Register Indirect | 4(1/0) | 8(2/0) |
(An)+ | Address Register Indirect with post-increment | 4(1/0) | 8(2/0) |
d(An) | Address Register Indirect with displacement | 8(2/0) | 12(3/0) |
d(An, ix) | Address Register Indirect with index | 10(2/0) | 14(3/0) |
#xxx.W | Absolute Short | 8(2/0) | 12(3/0) |
#xxx.L | Absolute Long | 12(3/0) | 16(4/0) |
d(PC) | Program Counter with displacement | 8(2/0) | 12(3/0) |
d(PC, ix) | Program Counter with index | 10(2/0) | 14(3/0) |
#xxx | Immediate | 4(1/0) | 8(2/0) |
Move Instruction Execution Times
Note: The size of the index register (ix) does not affect the instruction execution time.
Byte and Word
Dn | An | (An) | (An)+ | -(An) | d(An) | d(An, ix) | #xxx.W | #xxx.L | |
---|---|---|---|---|---|---|---|---|---|
Dn | 4(1/0) | 4(1/0) | 8(1/1) | 8(1/1) | 8(1/1) | 12(2/1) | 14(2/1) | 12(2/1) | 16(3/1) |
An | 4(1/0) | 4(1/0) | 8(1/1) | 8(1/1) | 8(1/1) | 12(2/1) | 14(2/1) | 12(2/1) | 16(3/1) |
(An) | 8(2/0) | 8(2/0) | 12(2/1) | 12(2/1) | 12(2/1) | 16(3/1) | 18(3/1) | 16(3/1) | 20(4/1) |
(An)+ | 8(2/0) | 8(2/0) | 12(2/1) | 12(2/1) | 12(2/1) | 16(3/1) | 18(3/1) | 16(3/1) | 20(4/1) |
-(An) | 10(2/0) | 10(2/0) | 14(2/1) | 14(2/1) | 14(2/1) | 18(3/1) | 20(4/1) | 18(3/1) | 22(4/1) |
d(An) | 12(3/0) | 12(3/0) | 16(3/1) | 16(3/1) | 16(3/1) | 20(4/1) | 22(4/1) | 20(4/1) | 24(5/1) |
d(An, ix) | 14(3/0) | 14(3/0) | 18(3/1) | 18(3/1) | 18(3/1) | 22(4/1) | 24(4/1) | 22(4/1) | 26(5/1) |
#xxx.W | 12(3/0) | 12(3/0) | 16(3/1) | 16(3/1) | 16(3/1) | 20(4/1) | 22(4/1) | 20(4/1) | 24(5/1) |
#xxx.L | 16(4/0) | 16(4/0) | 20(4/1) | 20(4/1) | 20(4/1) | 24(5/1) | 26(5/1) | 24(5/1) | 28(6/1) |
d(PC) | 12(3/0) | 12(3/0) | 16(3/1) | 16(3/1) | 16(3/1) | 20(4/1) | 22(4/1) | 20(4/1) | 24(5/1) |
d(PC, ix) | 14(3/0) | 14(3/0) | 18(3/1) | 18(3/1) | 18(3/1) | 22(4/1) | 24(4/1) | 22(4/1) | 26(5/1) |
#xxx | 8(2/0) | 8(2/0) | 12(2/1) | 12(2/1) | 12(2/1) | 16(3/1) | 18(3/1) | 16(3/1) | 20(4/1) |
Longword
Dn | An | (An) | (An)+ | -(An) | d(An) | d(An, ix) | #xxx.W | #xxx.L | |
---|---|---|---|---|---|---|---|---|---|
Dn | 4(1/0) | 4(1/0) | 12(1/2) | 12(1/2) | 12(1/2) | 16(2/2) | 18(2/2) | 16(2/2) | 20(3/2) |
An | 4(1/0) | 4(1/0) | 12(1/2) | 12(1/2) | 12(1/2) | 16(2/2) | 18(2/2) | 16(2/2) | 20(3/2) |
(An) | 12(3/0) | 12(3/0) | 20(3/2) | 20(3/2) | 20(3/2) | 24(4/2) | 26(4/2) | 24(4/2) | 28(5/2) |
(An)+ | 12(3/0) | 12(3/0) | 20(3/2) | 20(3/2) | 20(3/2) | 24(4/2) | 26(4/2) | 24(4/2) | 28(5/2) |
-(An) | 14(3/0) | 14(3/0) | 22(3/2) | 22(3/2) | 22(3/2) | 26(4/2) | 28(4/2) | 26(4/2) | 30(5/2) |
d(An) | 16(4/0) | 16(4/0) | 24(4/2) | 24(4/2) | 24(4/2) | 28(5/2) | 30(5/2) | 28(5/2) | 32(6/2) |
d(An, ix) | 18(4/0) | 18(4/0) | 26(4/2) | 26(4/2) | 26(4/2) | 30(5/2) | 32(5/2) | 30(5/2) | 34(6/2) |
#xxx.W | 16(4/0) | 16(4/0) | 24(4/2) | 24(4/2) | 24(4/2) | 28(5/2) | 30(5/2) | 28(5/2) | 32(6/2) |
#xxx.L | 20(5/0) | 20(5/0) | 28(5/2) | 28(5/2) | 28(5/2) | 32(6/2) | 34(6/2) | 32(6/2) | 36(7/2) |
d(PC) | 16(4/0) | 16(4/0) | 24(4/2) | 24(4/2) | 24(4/2) | 28(5/2) | 30(5/2) | 28(5/2) | 32(5/2) |
d(PC, ix) | 18(4/0) | 18(4/0) | 26(4/2) | 26(4/2) | 26(4/2) | 30(5/2) | 32(5/2) | 30(5/2) | 34(6/2) |
#xxx | 12(3/0) | 12(3/0) | 20(3/2) | 20(3/2) | 20(3/2) | 24(4/2) | 26(4/2) | 24(4/2) | 28(5/2) |
Standard Instruction Execution Times
The number of processor clocks shown in this table indicate the time required to perform the operations, store the results, and to read the next instruction. When indicated by a +, the effective address calculation time must be added to the time required for the instruction itself.
Headings in the table have the following meanings:
- An = Address register operand
- Dn = Data register operand
- ea = Operand specified by effective address
- M = Memory operand
Size | op<ea>, An^ | op<ea>, Dn | op Dn, <M> | |
---|---|---|---|---|
ADD | B, W | 8(1/0)+ | 4(1/0)+ | 8(1/1)+ |
L | 6(1/0)+** | 6(1/0)+** | 12(1/2)+ | |
AND | B, W | - | 4(1/0)+ | 8(1/1)+ |
L | - | 6(1/0)+** | 12(1/2)+ | |
CMP | B, W | 6(1/0)+ | 4(1/0)+ | - |
L | 6(1/0)+ | 6(1/0)+ | - | |
DIVS | - | - | 158(1/0)+* | - |
DIVU | - | - | 140(1/0)+* | - |
EOR | B, W | - | 4(1/0)*** | 8(1/1)+ |
L | - | 8(1/0)*** | 12(1/2)+ | |
MULS | - | - | 70(1/0)+* | - |
MULU | - | - | 70(1/0)+* | - |
OR | B, W | - | 4(1/0)+ | 8(1/1)+ |
L | - | 6(1/0)+** | 12(1/2)+ | |
SUB | B, W | 8(1/0)+ | 4(1/0)+ | 8(1/1)+ |
L | 6(1/0)+** | 6(1/0)+** | 12(1/2)+ |
- +: Add effective address calculation time to specified instruction execution time.
- ^: Word or long only
- *: Maximum value (worst case)
- **: Base time of six clocks is increased to eight if the effective address mode is register direct or immediate (effective address calculation time should also be added)
- ***: The only available effective address mode is data register direct
DIVS and DIVU
The divide algorithm that is implemented in the 68000 gives a less than 10% time difference between best and worst case timings.
MULS and MULU
The multiplication algorithm implemented requires 38+2n
clocks, where n is defined as:
- MULU: n = the number of ones in the <ea>
- MULS: n = concatanate the <ea> with a zero as the LSB; n is the resultant number of 10 or 01 patterns in the 17-bit source; i.e., worst case happens when the source is
$5555
Immediate Instruction Execution Times
The number of processor clocks shown in this table indicate the time required to fetch the immediate operands, perform the operations, store the results, and to read the next instruction. When indicated by a +, the effective address calculation time must be added to the time required for the instruction itself.
Size | op #, Dn | op #, An | op #, <M> | |
---|---|---|---|---|
ADDI | B, W | 8(2/0) | - | 12(2/1)+ |
L | 16(3/0) | - | 20(3/2)+ | |
ADDQ | B, W | 4(1/0) | 8(1/0)* | 8(1/1)+ |
L | 8(1/0) | 8(1/0) | 12(1/2)+ | |
ANDI | B, W | 8(2/0) | - | 12(2/1)+ |
L | 16(3/0) | - | 20(3/1)+ | |
CMPI | B, W | 8(2/0) | - | 8(2/0)+ |
L | 14(3/0) | - | 12(3/0)+ | |
EORI | B, W | 8(2/0) | - | 12(2/1)+ |
L | 16(3/0) | - | 20(3/2)+ | |
MOVEQ | L | 4(1/0) | - | - |
ORI | B, W | 8(2/0) | - | 12(2/1)+ |
L | 16(3/0) | - | 20(3/2)+ | |
SUBI | B, W | 8(2/0) | - | 12(2/1)+ |
L | 16(3/0) | - | 20(3/2)+ | |
SUBQ | B, W | 4(1/0) | 8(1/0)* | 8(1/1)+ |
L | 8(1/0) | 8(1/0) | 12(1/2)+ |
- +: Add effective address calculation time to specified instruction execution time.
- ^: Word only
Single Operand Instruction Execution Times
The number of processor clocks shown in this table indicate the time required for the single operand instructions. When indicated by a +, the effective address calculation time must be added to the time required for the instruction itself.
Size | Register | Memory | |
---|---|---|---|
CLR | B, W | 4(1/0) | 8(1/1)+ |
L | 6(1/0) | 12(1/2)+ | |
NBCD | B | 6(1/0) | 8(1/1)+ |
NEG | B, W | 4(1/0) | 8(1/1)+ |
L | 6(1/0) | 12(1/2)+ | |
NEGX | B, W | 4(1/0) | 8(1/1)+ |
L | 6(1/0) | 12(1/2)+ | |
NOT | B, W | 4(1/0) | 8(1/1)+ |
L | 6(1/0) | 12(1/2)+ | |
SCC | B, false | 4(1/0) | 8(1/1)+ |
B, true | 6(1/0) | 8(1/1)+ | |
TAS | B | 4(1/0) | 10(1/1)+ |
TST | B, W | 4(1/0) | 4(1/0)+ |
L | 4(1/0) | 4(1/0)+ |
- +: Add effective address calculation time to specified instruction execution time.
Rotate Instruction Execution Times
The number of processor clocks shown in this table indicate the time required for the shift and rotate instructions. When indicated by a +, the effective address calculation time must be added to the time required for the instruction itself.
Size | Register | Memory | |
---|---|---|---|
ASR, ASL | B, W | 6+2n(1/0) | 8(1/1)+ |
L | 8+2n(1/0) | - | |
LSR, LSL | B, W | 6+2n(1/0) | 8(1/1)+ |
L | 8+2n(1/0) | - | |
ROR, ROL | B, W | 6+2n(1/0) | 8(1/1)+ |
L | 8+2n(1/0) | - | |
ROXR, ROXL | B, W | 6+2n(1/0) | 8(1/1)+ |
L | 8+2n(1/0) | - |
- +: Add effective address calculation time to specified instruction execution time.
-
n
is the shift or rotate count